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    • 专利摘要:
    Excerpt Method for detecting a photocurrent A method of use of a photocurrent detection circuit is presented, this detection circuit comprising a photodiode (1), pixel amplifier (2) and MOS transistor (3), the photodiode being connected to a pixel amplifier input (2) and the MOS transistor is connected between the pixel amplifier input and a pixel amplifier output. The method includes - applying current output from the pixel amplifier to the MOS transistor (3) causing the output current to form a current between MOS transistor drain and source, the MOS transistor getting gate voltage VLOG until the current between drain and source equilibrated is with the photocurrent, utilizing the logarithmic part of a gate-to-source voltage characteristic as a function of the current between drain and source.
    公开号:BE1021022B1
    申请号:E2014/0289
    申请日:2014-04-25
    公开日:2014-12-19
    发明作者:Bogget Urbain Van
    申请人:Xenics Nv；
    IPC主号:
    专利说明:

    Method of detecting a photocurrent Scope of the invention The present invention is mainly related to the scope of detection circuits, in particular detection circuits for infrared applications.
    Background of the Invention Imaging wavelength makers are made in the art with both linear and logarithmic responses. A linear response is obtained by simply charging a photosensitive silicon diode eigencapacity while there is a bias voltage in inversely polarized direction. A logarithmic response is achieved by adding a MOS transistor connected to a diode to the photodiode output and using the logarithmic characteristic of the transistor thus connected to obtain the logarithmic compression. Both types essentially use the so-called "Source Follower per Detector" (SFD) method to isolate the low voltage stored in the photodiode or an additional holding capacitor to lead it to highly capacitive charged column nodes.
    This relatively simple concept can be used with silicon-based detectors for visible wavelengths because the leakage of these silicon diodes is still very low even at normal uncooled operating temperatures, and the change in reverse bias voltage will therefore only have a marginal influence on the signal .
    In infrared applications, however, the photodiodes are made from other materials, which leads to much higher leakage currents equivalent to a smaller leakage resistance that is connected in parallel with the detectors. The simple charging of the capacitor connected in parallel with the diode is therefore no longer practically usable at uncooled operating temperatures. An amplifier is therefore generally used to keep the reverse voltage of the photodiode constant and as close as possible to the zero bias to minimize the effect of the photodiode leakage resistance. The negative feedback element that stabilizes the amplifier can be a resistor or a capacitor. The resistance feedback is never used in practical pixel arrays as they are built today, because very large linear resistance values are required for the pixel to be sensitive. These large resistors are not compatible with the pixel size and the volume of CMOS processes used. Therefore, a small capacitor is generally used to achieve a dynamic operation similar to a shutter in a photochemical film camera. The amplifier is therefore generally called Capacitive Trans Impedance Amplifier (Amplifier) (CTIA). A special advantage of a CTIA is that the gain (expressed in Volts / electron) is adjustable by only changing the integration time. In this way the photo film and shutter speed settings are simulated.
    A focal plane array comprises various individual detector elements (pixels). The number of pixels in a linear or focal plane array is increasing. The signal multiplexer is a detector-specific integrated circuit with high complexity, which reads all pixels serially but also in parallel via multiple channels. In a commonly used detector circuit, the aforementioned capacitive feedback transimpedance amplifier (CTIA) is used to collect the detector current. The amplifier keeps the detector on virtual ground voltage while the detector current flows into the capacitor, thereby generating a voltage signal on the output that is proportional to the integration time and the signal current.
    However, there are limitations to the settings that are applied to the CTIA. The dynamic range is in any case limited by the ratio between the largest unsaturated output and the noise level. The response of these CTIA pixel amplifiers is linear and practically incompatible with very high photo currents that require a so-called well capacity and sufficient supply voltage to prevent saturation.
    Patent application US2011 / 068860 describes a detection circuit with an improved anti-blooming circuit. The detection circuit comprises a photodiode connected to an input of a capacitive transimpedance amplifier (CTIA). When the photodiode receives too intense light radiation, a so-called blooming effect on adjacent photodiodes of the linear or focal plane array occurs. This effect is due to the fact that the voltage difference at the capacitor ends of the CTIA then becomes so high that the photodiode bias voltage is affected. This change in the bias leads to a modification of the photon collection surface in the adjacent photodiodes. The blooming effect per se is well known in the art and is typically counteracted by providing a transistor parallel to the ends of the capacitor. The transistor prevents the photodiode from changing the bias voltage, while not preventing the capacitor from storing an amount of charge necessary for the exposure of the sensed image. In US2011 / 068860, the proposed solution comprises an anti-blooming circuit comprising a field effect transistor between the input and an output of the CTIA. The transistor is of the pMOS type when the CTIA input is connected to a cathode of the photodiode and of the nMOS type when the CTIA input is connected to an anode of the photodiode. The anti-blooming circuit comprises a means for comparing the voltage at the output of the CTIA with a setpoint voltage, the means for comparing being connected to a means for applying a feedback current to the CTIA input when the difference between the output voltage and the setpoint voltage reaches a limit value.
    US2011 / 068860 thus learns to define when the transistor is on or off depending on the difference between the setpoint voltage and the output voltage of the amplifier. If this difference is below a threshold, the transistor is in the off state, and if it is above that threshold, it is in the on state. However, the transistor cannot be seen as a purely logical switch that switches on at a certain threshold value Vt. The circuit proposed in US2011 / 068860 therefore delivers a performance that is considerably below the optimum.
    Therefore, there is a need for a solution in which the detection circuit gives an improved performance and in which properties of the components of the circuit are better utilized. Furthermore, there is a need for a circuit that allows the extraction of information from pixels that are sensitive to being affected by blooming.
    Summary of the Invention It is an object of embodiments of the present invention to provide a detection circuit that can be used operationally in a wider usable detector current range than the aforementioned prior art solutions.
    The above object is achieved by the solution of the present invention.
    In a first aspect, the invention relates to a method for using a photo current detection circuit, said detection circuit comprising a photo diode, a pixel amplifier and a MOS transistor with a gate, a source and a drain, wherein the photodiode is connected to an input of a pixel amplifier and the MOS transistor is connected between the input of the pixel amplifier and an output of the pixel amplifier. The method comprises the following steps - exposing the photo diode, which produces a photo current, - applying an input voltage to the pixel amplifier, the input voltage being derived from the photo current, - applying a current output from the pixel amplifier to the MOS transistor through which the output current forms a current between the drain and source of the MOS transistor, the MOS transistor on the gate being provided with a gate voltage until the current between the drain and source is substantially in balance with the photo current, utilizing a logarithmic portion of a gate-to-source voltage characteristic as a function of the current between the drain and source of the MOS transistor to obtain a voltage on the pixel amplifier output that is a logarithmic function of the photocurrent.
    The manner of operation described above does indeed make better use of the properties of the MOS transistor, whereby an improved performance of the detection circuit is obtained. A voltage signal is derived from the photo current, e.g. by charging the own capacitances of the input node comprising the sum of the detector own capacitance, amplifier input capacitance, optionally reset switch capacitance, and the MOS transistor capacitance input to the pixel amplifier. A current is obtained at the amplifier output which is connected to the source of the MOS transistor. The MOS transistor gate is supplied with a fixed gate voltage that is selected to prevent the amplifier output from reaching the bus power supply and thus saturating, thereby losing its transconductivity amplification characteristics.
    In one embodiment, the MOS transistor is an NMOS transistor. In another embodiment, the MOS transistor is a PMOS transistor depending on the polarity of the detector current.
    In a preferred embodiment, the pixel amplifier is a capacitive transimpedance amplifier.
    In an advantageous embodiment, the operation may be continuous that does not require a reset. The detection circuit can also be provided with a reset switch, which may also be implemented with an MOS transistor.
    In a preferred embodiment, the method comprises a step of pulsing the gate voltage to a bus power supply so that a reset function is achieved.
    In an advantageous embodiment, the logarithmic portion of the gate-to-source voltage characteristic has a slope of about 60mV / input current decade at room temperature as a function of the current between the drain and source.
    In another aspect, the invention relates to a method for calibrating a detection circuit for detecting photo current, said detection circuit comprising a photodiode, a pixel amplifier and a MOS transistor with a gate, a source and a drain, wherein the photodiode is connected to an input of a pixel amplifier and the MOS transistor is connected between the input of the pixel amplifier and an output of the pixel amplifier, the method comprising the steps of - selecting a transistor gate voltage level where saturation of the output of the pixel amplifier is prevented, - increasing the level of exposure applied to the photodiode until saturation of the output from the pixel amplifier is reached, - slowly reducing the level of exposure by a given step, the output of the amplifier is modified according to a logarithmic characteristic of a gate t-to-source voltage as a function of a drain source current of the MOS transistor, with a substantially constant amount until an output variation is observed that is substantially greater than the substantially constant amount, causing levels of illumination corresponding to a change of the output with the substantially constant amount, determine a logarithmic range.
    In the proposed calibration method, the exposure level is first determined at which the pixel amplifier output is saturated. Then the level of exposure is slowly reduced, each time with the same percentage. The amplifier output is thereby changed by a more or less constant amount as long as one stays in the logarithmic working range. Once a substantially greater output variation is observed for a reduced level of exposure, it is known that one has reached the linear range, beyond the logarithmic operating range.
    In another aspect, the invention also relates to a photo current detection circuit comprising a photo diode, a pixel amplifier and a MOS transistor with a gate, a source and a drain, the photo diode being connected to an input of a pixel amplifier and the MOS transistor is connected between the input of the pixel amplifier and an output of the pixel amplifier, the detection circuit being calibrated with the method of calibration as previously described.
    In one embodiment, the photo circuit detection circuit has a differential implementation.
    The invention also relates to an array of pixels comprising a plurality of detection circuits as described.
    For the purpose of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described above. Of course, it is to be understood that not all such goals or advantages can be achieved in accordance with any particular embodiment of the invention. The person skilled in the art will thus, for example, recognize that the invention can be designed or implemented in a manner that achieves or optimizes one advantage or group of advantages as indicated herein without necessarily achieving other objectives or advantages as may be indicated or proposed here.
    The above and other aspects of the invention will be apparent from and explained with reference to the embodiment (s) described below.
    BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be further described, by way of example, with reference to the accompanying drawings, wherein the same reference numbers refer to the same elements in the various figures.
    FIG. 1 shows the logarithmic behavior of the source voltage (if applied to gate IV) as a function of the current between drain and source of an NMOS transistor.
    FIG. 2 shows an embodiment of the circuit according to the present invention with an NMOS transistor and a P-diffusion anode photo diode connected to the amplifier input.
    FIG. 3 shows an embodiment of the circuit according to the present invention with a PMOS transistor and an N-diffusion cathode photodiode connected to the amplifier input.
    FIG. 4 shows an embodiment of the circuit of the invention with an NMOS transistor and a reset switch and a P-diffusion anode photo diode connected to the amplifier input.
    FIG. 5 shows an embodiment of the circuit of the invention with a PMOS transistor and a reset switch and an N-diffusion cathode photodiode connected to the amplifier input.
    FIG. 6 shows a possible single-end implementation of the inverting amplifier shown in the previous figures.
    FIG. 7 represents another possible single-end implementation of the inverting amplifier shown in the previous figures.
    FIG. 8 shows a possible differential implementation of the inverting amplifier shown in Figures 2 to 5.
    FIG. 9 shows another possible differential implementation of the inverting amplifier shown in Figures 2 to 5.
    FIG. 10 shows the behavior of the amplifier output voltage as a function of time for a number of photo current values.
    Detailed Description of Illustrative Embodiments The present invention will be described in relation to certain embodiments and with reference to certain drawings, but the invention is not limited thereto but only by the claims.
    Furthermore, the terms first, second and the like in the description and in the claims are used to distinguish between comparable elements and not necessarily for a sequence, or in time, in space, in arrangement or in any other describe it in a manner that It is to be understood that the terms so used are interchangeable under suitable conditions and that the embodiments of the invention described herein are capable of operating in a different order than described or shown herein.
    It is to be noted that the term "comprising" used in the claims is not to be construed as limiting the means mentioned thereafter; it does not exclude other elements or steps. It must therefore be interpreted as specifying the presence of the stated characteristics, integers, steps or components after which reference is made, but does not exclude the presence or addition of one or more other characteristics, integers, steps or components, or groups thereof . The scope of the expression "a device comprising means A and B" should therefore not be limited to devices consisting of components A and B only. It means that with regard to the present invention, the only relevant components of the device A and B are.
    Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or feature described in connection with the embodiment is part of at least one embodiment of the present invention. The appearance of the expressions "in one embodiment" or "in an embodiment" at different places throughout this specification therefore does not necessarily all refer to the same embodiment, but it is possible. Furthermore, the particular features, structures or properties may be combined in any suitable manner, as will be apparent to those skilled in the art from this disclosure, in one or more embodiments.
    Similarly, it should be appreciated that in the description of examples of embodiments of the invention, various features of the invention are sometimes grouped in a single embodiment, figure, or description thereof for the purpose of streamlining the description and assisting in understanding of one or more of the various resourceful aspects. However, this method of digestion should not be interpreted as an intention to reflect that the claimed invention requires more features than is explicitly enumerated in each claim. Rather, as the subsequent claims reflect, resourceful aspects are based on fewer than all of the features of a single preceding unlocked embodiment. Thus, the claims following the detailed description are hereby expressly incorporated in this detailed description, wherein each claim stands on its own as a separate embodiment of the present invention.
    Further, while some embodiments described herein include some but no other features that are part of other embodiments, combinations of features of different embodiments are considered to fall within the scope of the invention, and form different embodiments, as understood by those skilled in the art will be. For example, in the following claims, any of the embodiments claimed may be used in any combination.
    It should be noted that the use of particular terminology in describing certain features or aspects of the invention should not be construed to imply that the terminology is redefined here to be limited to embracing any specific property of the features or aspects of the invention with which that terminology is associated.
    Numerous specific details are set forth in the description herein. It should be understood, however, that embodiments of the invention can be applied without these specific details. In other cases, well-known methods, structures and techniques have not been shown in detail in order not to obscure the clarity of this description.
    Generally speaking, CMOS imagers have to deal with very small currents and therefore they work most naturally in a sub-threshold or weak inversion mode. The present invention responds to the logarithmic properties that an MOS transistor shows. This is especially true in the sub-threshold area or in weak inversion mode, where the response is constant and is close to about 60 mV per decade of source and drain current at room temperature.
    FIG. 1 shows the voltage at the source of an NMOS transistor when a voltage of IV is applied to its gate as a function of the source drain current. The latter is displayed using a logarithmic scale. Over a large range there is a linear relationship between source voltage and the logarithm of the current between source and drain. This range is supposed to be in sub-threshold or weak inversion mode. For larger current values, a deviation from the linear relationship becomes noticeable; this is the zone of strong inversion.
    Various statements in the above-mentioned patent application US2011 / 068860 make it clear that it is assumed that the MOS transistor has only two states, Off state below a gate to source threshold voltage Vt, and On state above the gate to source voltage Vt. This means that the logarithmic property of the gate-to-source voltage as a function of source-to-drain current is not considered at all and the possibilities it offers are indeed not exploited. Patent application US2011 / 068860 also completely ignores an important requirement for correct operation, namely that the current bias of the amplifier must be sufficiently high compared to the highest expected photocurrent.
    In the present invention, the pixel amplifier uses the exponential drain source current as a function of gate voltage or the logarithmic gate-to-source voltage as a function of the drain and source current characteristic of a CMOS transistor which is connected as the negative feedback and usually in weak inversion works. The gate has a bias voltage selected in such a way that saturation of the amplifier output is prevented. The source is connected to the amplifier output and the drain to the inverting input.
    Sub-threshold or weak inversion effect is not an absolute requirement for the present invention to be useful. However, it should be mentioned that in the strong inversion area that may be achieved in the very exceptional cases that the pixel bias would be set to very high values to accept extremely large photo streams, the subsequent data manipulation that may be required is much more complex due to the less predictable behavior of the detection circuit.
    When the photodiode anode is connected to the amplifier input, the feedback transistor must be of the NMOS type. In this case, the photocurrent flowing into the inverting input of the amplifier forces the amplifier output voltage to decrease until the gate-to-source voltage of the feedback NMOS (after a short stabilization time) reaches a value at which the current flows from drain to source is equal to the photo stream. At that point, the amplifier no longer supplies power to the output node. The amplifier output lowers about 60 mV as the photocurrent increases a decade at room temperature.
    In the case that the photodiode cathode is connected to the amplifier input, the feedback transistor must be of the PMOS type. The photocurrent flowing from the inverting input of the amplifier then forces the amplifier output voltage to increase until the gate-to-source voltage of the feedback PMOS (after a short stabilization time) reaches a value where the current flowing from drain to source equals the photo stream is. The amplifier is balanced. The amplifier output will change approximately 60 mV / decade increase in photocurrent at room temperature. The change in the input voltage of the amplifier as a function of the photo current is significantly reduced by the open-loop voltage gain of the amplifier. The incoming photocurrent is limited by the value of the current bias of the amplifier because the amplifier must at least be able to drain the photocurrent to one of the rail power supplies.
    Various embodiments of the circuit according to the invention are now described in more detail.
    FIG. 2 shows one pixel of an array operating in continuous mode (i.e., without reset option) in the event that the detector anode is connected to the pixel amplifier input. A plurality of such pixels arranged in horizontal and vertical directions are normally taken to form a linear or focal plane pixel array. As in FIG. 2, the photocurrent generated by the exposure of the photodiode 1 flows to the input node 4 of the amplifier 2 where it causes the input voltage to be slightly increased. Because of the gain of the amplifier, this leads to an amplified voltage drop from the output node 5 of amplifier 2. The amplifier 2 is typically an inverting amplifier. The amplifier 2 is an operational transconductance amplifier (OTA), i.e. an amplifier which converts an input voltage into an output current. The drop of the output voltage caused by the output current is applied to the source of the NMOS transistor 3 and causes the transistor conduction to start before the amplifier output reaches saturation if a suitable bias voltage VLOG is applied to its gate. The input node 4 is thus pulled down until no more current flows to the amplifier input and stabilizes. Note that in FIG. 2 Vss and Vdci mean the negative and positive supply voltages, respectively. Because of the logarithmic characteristic of the drain-source voltage as a function of the drain-source current of the NMOS transistor 3, the amplifier output will stabilize at a voltage value that falls back by approximately 60 mV (near room temperature) when the photocurrent is multiplied by 10, so one decade. Thus, for a range of input currents of 6 decades, the output voltage is expected to change to a range of only about 360 mV. The input voltage of the amplifier, on the other hand, will only increase by approximately 360 mV divided by the gain of the amplifier. As long as the detector photocurrent is lower than say 1/10 or less of the current bias of the amplifier, it can be expected that the input voltage changes only less than a few mV. The inverse bias of the detector can be minimized in such a way without risk that it enters forward bias mode where it loses efficiency. The photocurrent flows to the amplifier output through the transistor, so the amplifier must be able to draw that current to ground (in this specific case) for the circuit to work properly. The power presetting of the amplifier must be at least higher than the incoming photo stream to prevent the amplifier from saturating.
    An important advantage of utilizing this logarithmic response and its obtained limited fluctuation of the amplifier output voltage is that the so-called analog power supply voltage can be significantly reduced, leading to less power consumption and reduced operational temperature of the device itself leading to a lower leakage current of the photo diode. This aspect is of primary importance because it allows operation under the worst environmental conditions and / or allows for simpler camera designs, possibly without or with limited artificial cooling. It also allows the use of standard digital CMOS technologies with limited power supply options.
    FIG. 3 shows one pixel operating in continuous mode without reset in case the cathode of the detector is connected to the pixel amplifier input. As already mentioned, the transistor is then of the PMOS type. A plurality of such pixels arranged in horizontal and vertical directions are normally taken to form a so-called linear or focal plane pixel array. The operation of this circuit is comparable to that of FIG. 2, only the polarities are reversed.
    In a preferred embodiment, the amplifier 2 is a capacitive transimpedance amplifier (CTIA).
    FIG. 4 shows one pixel of an array operating in CTIA mode combined with an extended usable logarithmic range in case the anode of the detector 1 is connected to the pixel amplifier input. The usual CTIA range is used for small photo currents in a linear range as a function of the integration time to a certain integration time value where the current taken by transistor 3 becomes greater than the current flowing in the CTIA integration capacitor.
    In the embodiment of FIG. 4, the amplifier is a capacitive transmission amplifier (CTIA) with a capacitive feedback 6. Furthermore, a reset switch 7 is provided. The reset switch is usually also implemented with an MOS transistor. In this case, the bias voltages are set so that the MOS transistor 3 does not conduct yet after the CTIA reset has been performed. Input current from the detector diode 1 flowing to the input of amplifier 2 tends to lower the output voltage, which in turn causes the current to flow into the feedback capacitor 6 until output node 5 reaches a value low enough to cause transistor 3 to start conducting to become. At that point, transistor 3 will set the voltage of output node 5 to a value that is dependent on the input current value but compressed to a 60 mV / input current decade format. This means that if the CTIA is set to integrate for a limited time, for example 5 ms defined by the output amp time, one has two different output voltage zones. The lowest input currents from the detector are part of the normal linear zone of the CTIA, while the highest input currents from the detector are compressed to the 60 mV / input current decade format before the end of the integration time. See also FIG. 10 for the characteristic voltage on node 5 with different photo currents and an integration capacitor of 3 fF.
    FIG. 5 shows the counterpart of FIG. 3. A pixel operates in CTIA mode with extended range in the case that the cathode of the detector is connected to the pixel amplifier input. The operation of this circuit is comparable to that of FIG. 4, only the polarities are reversed.
    The function of the reset switch 7 shown in FIG. 4 and FIG. 5 can be replaced by pulsing the VLOG gate voltage to the bus power supply in a direction that forces the MOS transistor 3 to become more conductive. This can be advantageous in cases where the pixel size is critical.
    FIG. 6 and 7 show two examples of single-ended pixel amplifier implementations. In the examples shown, the amplifiers are transconductance amplifiers.
    FIG. 8 and 9 show two possible differential implementations of the pixel amplifier. Transconductance amplifiers are also used here, as is customary in this type of application.
    In practice, the invention allows a given image designer to be used in three different modes by setting only the bias voltages VLOG and sending signals to certain values: CTIA with variable integration time in non-saturated linear mode with correlated double sampling (CDS) for the highest sensitivity and lowest noise capture of possible moving objects in images with limited contrast - dynamic linear CTIA with very long integration time (cooled for infrared detectors) combined with extended mode with logarithmic compression range to capture the widest dynamic range of images with very little light combined with highly exposed areas. - continuous TIA mode with static pure logarithmic compression (without reset) for highly contrasting images with a wide dynamic range.
    In one aspect, the invention also relates to a method for calibrating the detection circuit when used in the combined linear CTIA and logarithmic extended mode. Since the calibration is influenced by the temperature, this parameter must be taken into account. A suitable single and longest possible integration time is specifically chosen to fit the frame rate within the execution of the calibration and the subsequent operational procedure, for example 5 milliseconds. This integration time will be applied throughout the entire calibration and subsequent operations. A practical transistor gate voltage is selected, i.e. at a level sufficiently high to prevent amplifier saturation. An iterative method is then followed, step by step increasing the level of exposure applied to the photodiode. This is repeated until saturation of the amplifier output or in the practical case of an array of detector circuits (pixels) saturation of all amplifier outputs of the array is achieved. This occurs when all outputs change less than -100 mV for an increase of 10x in exposure. Then the level of exposure is again reduced in small steps to, for example, 70% of the previous exposure level. Here, the amplifier output is changed according to a logarithmic function, each time with an amount of e.g. approximately +10 mV. The lowering of the exposure level is repeated until an output variation is observed that is substantially higher (e.g. +100 mV) than the previously observed substantially constant value of about 10 mV. The output values of these pixels are stored, which defines the transition value between linear and logarithmic working range for later data manipulation. Once the detection circuit (s) has been calibrated in this way, the detection circuit (s) are preferably operated at exposure ranges that cause photocurrent values that are less than about 1/10 of the selected current bias of the amplifier.
    FIG. 10 shows some simulation results that show the evolution of the CTIA amplifier output voltage over time when 1.2 V is applied to the gate. Results are given for a number of photo stream values. The figure shows that photocurrent values of 1012 A and higher are clearly within the logarithmic compression range, while smaller currents are in the linear zone of the characteristic. Note that an integration time of 5 ms was taken to get the displayed curves. Reduction of the integration time is not necessary to obtain information for higher levels of photo streams.
    While the invention has been shown and described in detail in the drawings and foregoing description, such illustration and description should be considered as illustrative or exemplary and not limiting. The foregoing description details certain embodiments of the invention. It will be appreciated, however, that regardless of how detailed the foregoing appears in text, the invention may be practiced in many ways. The invention is not limited to the described embodiments.
    Other variations in the described embodiments can be understood and practiced by those skilled in the art upon practicing the invention from a study of the drawings, the description and the appended claims. In the claims, the word "include" does not exclude other elements or steps, and the indefinite article "a" does not exclude a plural. A single processor or other unit can perform the functions of different items listed in the claims. The mere fact that certain measures are enumerated in mutually different dependent claims does not indicate that a combination of these measures cannot be advantageously applied. A computer program can be stored / distributed on a suitable medium, such as an optical storage medium or a solid state medium that is supplied together with or as part of other hardware, but can also be distributed in other forms, such as via the internet or other wired or wireless telecommunication systems . Each reference number in the claims is not to be construed as limiting the scope of protection.
    权利要求:
    Claims (12)
    [1]
    CONCLUSIONS
    A method for using a photocurrent detection circuit, said detection circuit comprising a photo diode (1), a pixel amplifier (2) and a MOS transistor (3) with a gate, a source and a drain, the photo diode having a input of a pixel amplifier (2) is connected and the MOS transistor is connected between the input of the pixel amplifier and an output of the pixel amplifier, the method comprising the steps of - illuminating the photo diode (1), which produces a photo current - applying an input voltage to the pixel amplifier (2), the input voltage being derived from the photo current, - applying a current output from the pixel amplifier to the MOS transistor (3), whereby the output current forms a current between the drain and source of the MOS transistor, the MOS transistor on the gate being supplied with a gate voltage (VLOG) until the current between the drain and source is substantially equal to the photo current, utilizing a logarithmic part of a gate-to-source voltage characteristic as a function of the current between the drain and source of the MOS transistor to obtain a voltage on the pixel amplifier output that is a logarithmic function of the photo current .
    [2]
    A method for using a detection circuit according to claim 1, wherein the MOS transistor is an NMOS transistor.
    [3]
    The method for using a detection circuit according to claim 1, wherein the MOS transistor is a PMOS transistor.
    [4]
    The method for using a detection circuit according to any of claims 1 to 3, wherein the pixel amplifier is a capacitive transimpedance amplifier.
    [5]
    A method for using a detection circuit according to any one of the preceding claims, wherein the detection circuit comprises a reset switch (7).
    [6]
    The method for using a detection circuit according to claim 5, wherein the reset switch is implemented with another MOS transistor.
    [7]
    A method for using a detection circuit according to any one of the preceding claims, comprising a step of pulsing the gate voltage (VLOG) on a rail power supply so that a reset function is achieved.
    [8]
    A method for using a detection circuit according to any one of the preceding claims wherein the logarithmic portion of the gate-to-source voltage characteristic has a slope of about 60 mV / photocurrent decade as a function of the current between the drain and source at room temperature.
    [9]
    A method for calibrating a detection circuit for detecting photocurrent, the detection circuit comprising a photodiode (1), a pixel amplifier (2) and a MOS transistor (3) with a gate, a source and a drain, the The photodiode is connected to an input of a pixel amplifier (2) and the MOS transistor is connected between the input of the pixel amplifier and an output of the pixel amplifier, the method comprising the steps of - selecting a transistor gate voltage (VLOG) level whereby saturation of the output of the pixel amplifier is prevented, - increasing the level of exposure applied to the photodiode until saturation of the output of the pixel amplifier is reached, - allowing the level of exposure to be slowly reduced by a given step in which the output of the amplifier is changed according to a logarithmic characteristic of a gate-to-source voltage as a function of e and drain source current of the MOS transistor, with a substantially constant amount until an output variation is observed that is substantially greater than the substantially constant amount, whereby levels of illumination corresponding to a change of the output with the substantially constant amount , determine a logarithmic range.
    [10]
    A detection circuit for detecting a photo stream comprising a photo diode (1), a pixel amplifier (2) and a MOS transistor (3) with a gate, a source and a drain, the photo diode having an input of a pixel amplifier ( 2) is connected and the MOS transistor is connected between the input of the pixel amplifier and an output of the pixel amplifier, whereby the detection circuit is calibrated with the calibration method according to claim 9.
    [11]
    11. Detection circuit for detecting a photo stream according to claim 11, which has a differential implementation.
    [12]
    An array of pixels comprising a plurality of detection circuits according to claim 9 or 10.
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    JP2009159610A|2009-07-16|Current sampling method and circuit
    TW201519420A|2015-05-16|Buffered direct injection pixel for infrared detector arrays
    JP2000162041A|2000-06-16|Photo-detection device
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    JP6484513B2|2019-03-13|Image sensor
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US5929434A|1997-08-13|1999-07-27|Rockwell Science Center, Llc|Ultra-low noise high bandwidth interface circuit for single-photon readout of photodetectors|
    JP4610075B2|2000-12-05|2011-01-12|ローム株式会社|Receiver|
    FR2950480B1|2009-09-22|2011-11-25|Soc Fr Detecteurs Infrarouges Sofradir|DETECTION CIRCUIT WITH IMPROVED ANTI-GLOWING CIRCUIT|JP2019054438A|2017-09-15|2019-04-04|アズビル株式会社|Photoelectric sensor|
    CN111201708A|2017-10-11|2020-05-26|浜松光子学株式会社|Differential amplifier, pixel circuit, and solid-state imaging device|
    RU2703823C1|2018-12-21|2019-10-22|Акционерное общество "ЛОМО"|Apparatus for amplification and preliminary processing of pulses from an infrared photodiode|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    EP131654915|2013-04-26|
    EP13165491.5A|EP2797228B1|2013-04-26|2013-04-26|Method for detecting a photocurrent|
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